On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > be changeable by changing the rate of PLL_CPUX. > > Add CLK_SET_RATE_PARENT flag to this clock. > > Signed-off-by: Icenowy Zheng <icenowy@xxxxxxxx> Acked-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
Attachment:
signature.asc
Description: PGP signature
