12.12.2016, 01:26, "Wolfram Sang" <wsa@xxxxxxxxxxxxx>: > On Tue, Nov 29, 2016 at 05:00:17PM -0800, Brendan Higgins wrote: >> Added initial master and slave support for Aspeed I2C controller. >> Supports fourteen busses present in ast24xx and ast25xx BMC SoCs by >> Aspeed. >> >> Signed-off-by: Brendan Higgins <brendanhiggins@xxxxxxxxxx> > > BTW first the bindings patch please, then the driver. > > And one seperate question I just stumbled over: > >> + /* Switch from master mode to slave mode. */ >> + func_ctrl_reg_val = aspeed_i2c_read(bus, ASPEED_I2C_FUN_CTRL_REG); >> + func_ctrl_reg_val &= ~ASPEED_I2CD_MASTER_EN; >> + func_ctrl_reg_val |= ASPEED_I2CD_SLAVE_EN; >> + aspeed_i2c_write(bus, func_ctrl_reg_val, ASPEED_I2C_FUN_CTRL_REG); > > Can't the hardware work both as master and slave on the same bus? The hardware can work as master and slave on the same bus. This is how IPMB over i2c works on Aspeed. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
