On 12/10/2016 06:18 PM, Cédric Le Goater wrote: > On 12/10/2016 05:03 AM, Marek Vasut wrote: >>> +/* >>> + * The AST2400 SPI flash controller does not have a CE Control >>> + * register. It uses the CE0 control register to set 4Byte mode at the >>> + * controller level. >>> + */ >>> +static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip) >>> +{ >>> + chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B; >>> + chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B; >> How do you know the SPI NOR is in 4B mode ? > > in aspeed_smc_chip_setup_finish() : > > if (chip->nor.addr_width == 4 && info->set_4b) > info->set_4b(chip); > Ahhh, great :) -- Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html