On Thu, 2016-12-08 at 12:42 +1030, Joel Stanley wrote:
> > On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@xxxxxxxx> wrote:
> > The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> > on bits in both the System Control Unit and the LPC Host Controller.
> >
> > The Aspeed LPC Host Controller is described as a child node of the
> > LPC host-range syscon device for arbitration of access by the host
> > controller and pinmux drivers.
> >
> > > > Signed-off-by: Andrew Jeffery <andrew@xxxxxxxx>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > index a97131aba446..9de318ef72da 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > > > @@ -109,3 +109,25 @@ lpc: lpc@1e789000 {
> > };
> > };
> >
> > +Host Node Children
> > +==================
> > +
> > +LPC Host Controller
> > +-------------------
> > +
> > +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> > +between the host and the baseboard management controller. The registers exist
> > +in the "host" portion of the Aspeed LPC controller, which must be the parent of
> > +the LPC host controller node.
> > +
> > +Required properties:
> > +- compatible: "aspeed,ast2500-lhc";
>
> Can you remind me why this binding doesn't cover the ast2400?
Partly that we haven't yet needed the LHC for the AST2400.
Mostly that I overlooked it.
If there are other problems with series I'll address this issue, but if
not we can add it when we need it down the track.
Andrew
>
> Cheers,
>
> Joel
>
> > +- reg: contains offset/length value of the LHC memory
> > + region.
> > +
> > +Example:
> > +
> > > > +lhc: lhc@20 {
> > + compatible = "aspeed,ast2500-lhc";
> > + reg = <0x20 0x24 0x48 0x8>;
> > +};
> > --
> > 2.9.3
> > Attachment:
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