Hi Richard, On 12/02/2016 03:58 AM, Richard Cochran wrote: > On Wed, Nov 30, 2016 at 11:17:38PM +0100, Richard Cochran wrote: >> On Wed, Nov 30, 2016 at 02:43:57PM -0600, Grygorii Strashko wrote: >>> Sry, but this is questionable - code for pps comes from TI internal >>> branches (SDK releases) where it survived for a pretty long time. > > Actually, there is a way to get an accurate PPS from the am335x. See > this recent thread: > > https://www.mail-archive.com/linuxptp-devel@xxxxxxxxxxxxxxxxxxxxx/msg01726.html > > That is the way to go, and so, please drop this present patch. > thanks for the links - it sounds very interesting. As I understood, people trying to enable PPS on am335 device with the goal to have PPS signal generated on some SoC pin and therefore they use DMtimer. Also, as i understood, the Timer Load Register (TLDR) is corrected once a second at each HW_TS_PUSH - as result, if freq was corrected during current sec there will be some HW_TS_PUSH generation jitter any way. Above solution is a bit complex for keystone 2 SoCs, as CPTS itself on these SoCs has output pin (ts_comp) which can be used for PPS signal generation. So, I think, similar results can be achieved by removing PPS correction code from cpts_ptp_adjfreq() and updating CPTS_TS_LOAD_VAL once a sec in cpts_overflow_check(). or I missed smth? -- regards, -grygorii -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
