Hi Jeremy, On 29/11/16 20:45, Jeremy Linton wrote:
The PCIe root complex on Juno translates the MMIO mapped at 0x5f800000 to the PIO address range starting at 0 (which is common because PIO addresses are generally < 64k). Correct the DT to reflect this.
I have another DT fix that I have asked ARM-SoC guys to pick up directly from the list. If that doesn't happen, I will send PR including both. If that happens then we need to send this to them to be picked directly. At this point I want to wait for couple of days to avoid confusion. -- Regards, Sudeep -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
