On Thu, Nov 24, 2016 at 5:01 PM, Jerome Brunet <jbrunet@xxxxxxxxxxxx> wrote: > On Thu, 2016-11-24 at 15:40 +0100, Martin Blumenstingl wrote: >> Hi Jerome, >> >> On Mon, Nov 21, 2016 at 4:35 PM, Jerome Brunet <jbrunet@xxxxxxxxxxxx> >> wrote: >> > >> > This patchset fixes an issue with the OdroidC2 board (DWMAC + >> > RTL8211F). >> > Initially reported as a low Tx throughput issue at gigabit speed, >> > the >> > platform enters LPI too often. This eventually break the link (both >> > Tx >> > and Rx), and require to bring the interface down and up again to >> > get the >> > Rx path working again. >> > >> > The root cause of this issue is not fully understood yet but >> > disabling EEE >> > advertisement on the PHY prevent this feature to be negotiated. >> > With this change, the link is stable and reliable, with the >> > expected >> > throughput performance. >> I have just sent a series which allows configuring the TX delay on >> the >> MAC (dwmac-meson8b glue) side: [0] >> Disabling the TX delay generated by the MAC fixes TX throughput for >> me, even when leaving EEE enabled in the RTL8211F PHY driver! >> >> Unfortunately the RTL8211F PHY is a black-box for the community >> because there is no public datasheeet available. >> *maybe* (pure speculation!) they're enabling the TX delay based on >> some internal magic only when EEE is enabled. > > Hi already tried acting on the register setting the TX_delay. I also > tried on the PHY. I never been able to improve situation on the > Odroic2. Only disabling EEE improved the situation. OK, thanks for clarifying this! > To make sure, i tried again with your patch but the result remains > unchanged. With Tx_delay disabled (either the mac or the phy), the > situation is even worse, it seems that nothing gets through This is interesting, because in your case you should have a 4ns TX delay (2ns from the MAC and presumably 2ns from the PHY). Maybe that is also the reason why the TX delay is configurable in 2ns steps in PRG_ETHERNET0 on Amlogic SoCs. out of curiosity: have you tried setting a 4ns (half clock-cycle) TX delay for the MAC and disabling it in the PHY? Regards, Martin -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
