> -----Original Message-----
> From: Harninder Rai
> Sent: Tuesday, November 15, 2016 12:15 PM
> To: 'Shawn Guo' <shawnguo@xxxxxxxxxx>
> Cc: devicetree@xxxxxxxxxxxxxxx; robh+dt@xxxxxxxxxx;
> mark.rutland@xxxxxxx; oss@xxxxxxxxxxxx; Bhaskar U
> <bhaskar.upadhaya@xxxxxxx>; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> Subject: RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
>
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
> >
> > It seems that the patch is not generated against mainline kernel. We
> > do not have fsl-ls1046a-qds.dtb target in mainline kernel.
> You already clarified in the following mail :)
>
> > > +
> > > + reg_1p8v: regulator@0 {
> >
> > Drop the unit-address from node name, and name it like regulator-1p8v.
> Ok. Will take care in V2
>
> > > +
> > > +&duart0 {
> >
> > Please sort labeled nodes alphabetically.
> Ok Sure
> >
> > > + status = "okay";
> > > +};
> > > +
> > > +&sai2 {
> > > + status = "okay";
> > > +};
> >
> > <snip>
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv8-timer";
> > > + /* Physical Secure PPI */
> > > + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Physical Non-Secure PPI */
> > > + <1 14 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Virtual PPI */
> > > + <1 11 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Hypervisor PPI */
> > > + <1 10 IRQ_TYPE_LEVEL_LOW>;
> >
> > The following form should be easier for read.
> >
> > interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure
> PPI */
> > <1 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-
> Secure PPI */
> > <1 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual PPI */
> > <1 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor PPI
> */
> >
> >
> Agreed. My bad. Will correct in v2
>
> > > + scfg: scfg@1570000 {
> > > + compatible = "fsl,ls1012a-scfg", "syscon";
> > > + reg = <0x0 0x1570000 0x0 0x10000>;
> > > + big-endian;
> > > + };
> >
> > Please sort these nodes with unit-address in order of the address.
ok
> >
> > Shawn
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