William On Sun, Nov 13, 2016 at 11:01 PM, William Wu <wulf@xxxxxxxxxxxxxx> wrote: > Since we needs to delay ~1ms to wait for 480MHz output clock > of USB2 PHY to become stable after turn on it, the delay time > is pretty long for something that's supposed to be "atomic" > like a clk_enable(). Consider that clk_enable() will disable > interrupt and that a 1ms interrupt latency is not sensible. > > The 480MHz output clock should be handled in prepare callbacks > which support gate a clk if the operation may sleep. > > Signed-off-by: William Wu <wulf@xxxxxxxxxxxxxx> > --- > drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
