On 11/09/2016 07:54 PM, Joel Holdsworth wrote: > On 09/11/16 11:39, Marek Vasut wrote: >> On 11/09/2016 07:37 PM, Joel Holdsworth wrote: >>> On 09/11/16 05:01, Marek Vasut wrote: >>>> On 11/08/2016 06:30 PM, Joel Holdsworth wrote: >>>>>>>> On the whole, I don't think the zero-length transfers are too >>>>>>>> egregiously bad, and all the alternatives seem worse to me. >>>>>>> >>>>>>> So why not turn the CS line into GPIO and just toggle the GPIO? >>>>>> >>>>>> Does that work with *all* SPI controllers? >>>>>> >>>>> >>>>> It does not - no. See my other email. >>>> >>>> And is that line an actual CS of that lattice chip or a generic input >>>> which almost works like CS? >>>> >>> >>> I mean a generic output vs. a special CS output built into the SPI >>> master of the application processor. Take a look at how spi_set_cs(..) >>> works: >> >> No. I am asking whether the signal which is INPUT on the iCE40 side is >> really a chipselect signal for the SPI bus OR something which mostly >> behaves/looks like a chipselect but is not really a chipselect. > > Oh I see. The SS_B line is the SPI SlaveSelect for the configuration port. > > This is the text from the datasheet: > > "SPI Slave Select. Active Low. Includes an internal weak pull-up > resistor to VCC_SPI during configuration. During configuration, the > logic level sampled on this pin deter-mines the configuration mode used > by the iCE40 device. An input when sampled at the start of > configuration. An input when in SPI Peripheral configuration mode > (SPI_SS_B = Low). An output when in Master SPI Flash configuration mode." > > So yes - it is a "real" SPI chip-select line. OK, thanks for checking. -- Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
