On Fri, Nov 4, 2016 at 8:59 PM, Grygorii Strashko <grygorii.strashko@xxxxxx> wrote: > On 11/04/2016 09:28 AM, Linus Walleij wrote: >> The DT model sort of mandates how the interrupts should be mapped >> at this point, and as far as I can tell from the binding the example looks >> like so: >> >> gpio: gpio@1e26000 { >> compatible = "ti,dm6441-gpio"; >> gpio-controller; >> #gpio-cells = <2>; >> reg = <0x226000 0x1000>; >> interrupt-parent = <&intc>; >> interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH >> 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH >> 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH >> 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH >> 50 IRQ_TYPE_EDGE_BOTH>; >> ti,ngpio = <144>; >> ti,davinci-gpio-unbanked = <0>; >> interrupt-controller; >> #interrupt-cells = <2>; >> }; > > Above, DT bindings models Davinci GPIO IP as monolithic GPIO controller > with N gpio pins, but internally separate GPIO chips are created for each > banksX&Y register set (32 pins, 2 banked irq -or- 32 direct irqs). Hm it would be good to get away from that and just have one big gpio chip. > Translation from linear GPIO numbering to the proper internal GPIO chip is done > using chip.of_xlate(). Yeah :/ this could be made simpler with a single chip just spanning all the banks and the common registers I think. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html