Hi Sergei,
On Thu, Oct 27, 2016 at 10:43 PM, Sergei Shtylyov
<sergei.shtylyov@xxxxxxxxxxxxxxxxxx> wrote:
> Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
> <geert+renesas@xxxxxxxxx>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@xxxxxxxxxxxxxxxxxx>
Thanks a lot for your patch!
> --- /dev/null
> +++ linux/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -0,0 +1,261 @@
> +static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
> + /* Core Clock Outputs */
> + DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1),
If you remove the "div = 3" in rcar-gen2-cpg.c, you can use "... 3, 1" here,
cfr. zg, zx, and zs below.
> + DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
> + DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
> + DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
> +static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
> + DEF_MOD("fdp1-1", 118, R8A7745_CLK_ZS),
FDP1-1 does not exist on RZ/G1E.
With these fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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