On Fri, Oct 14, 2016 at 7:20 AM, Tony Lindgren <tony@xxxxxxxxxxx> wrote: > * Jacek Anaszewski <j.anaszewski@xxxxxxxxxxx> [161013 23:37]: >> On 10/13/2016 04:20 PM, Matt Ranostay wrote: >> > On Thu, Oct 13, 2016 at 4:05 PM, Jacek Anaszewski >> > <j.anaszewski@xxxxxxxxxxx> wrote: >> > > Why DT property? Is it somehow dependent on the board configuration? >> > > How this period-scale value is calculated? Is it inferred empirically? >> > > >> > >> > We empirically discovered and verified this with an logic analyzer on >> > multiple batches of this part. >> > Reason for the DT entry is we aren't 100% sure that it is always going >> > to be the same with different board revs. >> > >> > Could be that parts clock acts differently with supply voltage. This >> > has been calculated by setting it an expected value, and measuring the >> > actual result with the logic analyzer. >> >> I'd like to have DT maintainer's ack for this. >> >> Cc Rob and Mark. > > How about do this based on the compatible property instead? If there > are multiple manufacturers for this part and only a certain > parts have this issue we should have multiple compatible properties. > I could only find that NXP as the manufacturer of that part. It is possible since the clock is internal to the chipset that the vdd of 2.5V is doing something undefined. > Then if it turns out all of them need this scaling there's no need > to update the binding. Understandable. > > Regards, > > Tony -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
