On Fri, Sep 16, 2016 at 7:05 PM, Stephen Boyd <stephen.boyd@xxxxxxxxxx> wrote: > Quoting Rob Herring (2016-09-16 08:19:51) >> On Wed, Sep 07, 2016 at 02:35:19PM -0700, Stephen Boyd wrote: >> > The high-speed phy on qcom SoCs is controlled via the ULPI >> > viewport. >> > [...] >> > +- qcom,init-seq: >> > + Usage: optional >> > + Value type: <u8 array> >> > + Definition: Should contain a sequence of ULPI register and address pairs to >> > + program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related >> > + to Device Mode Eye Diagram test. >> >> We generally nak this type of property. For 1 register I don't care so >> much. For 100, that would be another story. >> >> Is this value per unit, per board, per SoC? Can you limit it to certain >> registers? > > I'm told that this can be per board, depending on how it's wired from > the phy pins to the usb port. Typically it's the same though for the > boards I have, mostly because those boards are similar designs with > respect to how USB is wired. The set of registers is not that many, 4 or > 5 at most. My understanding is these are tuning registers. Right now the > register part in the binding is the full register offset, and not an > offset from ULPI_EXT_VENDOR_SPECIFIC (0x80). I could change this to be > an offset from that area if you like so that this can't be abused to > write into standard ULPI registers (there really isn't any way to > enforce this in software though). Okay, that sounds fine to me. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
