On 13/09/16 17:06, Archit Taneja wrote:
On 9/7/2016 4:25 PM, Srinivas Kandagatla wrote:
This patch adds support to msm8996 pcie phy which supports 3 ports,
Port A, Port B and Port C.
Each port is independent and connected to a pcie host controller,
there is
also a common block which is shared across all the 3 ports.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@xxxxxxxxxx>
---
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-qcom-msm8996-pcie.c | 492
++++++++++++++++++++++++++++++++++++
+#define PCIE_LANE_PCS_BASE 0x1400
I've seen the reg offsets of another SoC using the same
IP, but the above offsets aren't the same relative to the
phy base. We might want to create more reg properties in
DT to accommodate register maps on other SoCs.
Yep, I got some more info on this from Vivek and It looks like this IP
has been reused on other Host controllers and SOCs.
So plan is to write a common driver for all of them.
Thanks,
srini
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
