> Subject: Re: [PATCH] PCI: Xilinx NWL PCIe: Updating device tree documentation > with prefetchable memory space > > On Tue, Aug 09, 2016 at 07:30:09PM +0530, Bharat Kumar Gogada wrote: > > Updating device tree documentation with prefetchable memory sapce. > > Configuration space shifted to 64-bit address space. > > > > Signed-off-by: Bharat Kumar Gogada <bharatku@xxxxxxxxxx> > > --- > > Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > Acked-by: Rob Herring <robh@xxxxxxxxxx> Thanks Rob This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
