Hi, 2016-08-16 15:27 GMT+09:00 Chanwoo Choi <cw00.choi@xxxxxxxxxxx>: > From: Joonyoung Shim <jy0922.shim@xxxxxxxxxxx> > > This patch add the support of GPFx pin of Exynos5433 SoC. Exynos5433 has > different memory map of GPFx from previous Exynos SoC. Exynos GPIO has > following register to control gpio funciton. Usually, all registers of GPIO > are included in same domain. > - CON / DAT / PUD / DRV / CONPDN / PUDPDN > - EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND > > But, GPFx are included in two domain as following. So, this patch supports > the GPFx pin which handle the on separate two domains. > - ALIVE domain : CON / DAT / PUD / DRV / CONPDN / PUDPDN > - IMEM domain : EINT_CON/ EINT_FLTCON0, EINT_FLTCON1 / EINT_MASK / EINT_PEND I'm afraid I don't get anything from the description above. Could you describe the layout of registers in memory map and IRQ routing of the pins? Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
