On Fri, Aug 12, 2016 at 03:46:19PM +0530, Shubhrajyoti Datta wrote: > Some of the platforms like zynqmp ultrascale+ has a > separate clock gate for the rx clock. Add an optional > rx_clk so that the clock can be enabled. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> > --- > v2: > fix warning > > Documentation/devicetree/bindings/net/macb.txt | 2 +- > drivers/net/ethernet/cadence/macb.c | 31 +++++++++++++++++++++----- > drivers/net/ethernet/cadence/macb.h | 4 +++- > 3 files changed, 30 insertions(+), 7 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt > index b5a42df..315beda 100644 > --- a/Documentation/devicetree/bindings/net/macb.txt > +++ b/Documentation/devicetree/bindings/net/macb.txt > @@ -20,7 +20,7 @@ Required properties: > - phy-mode: See ethernet.txt file in the same directory. > - clock-names: Tuple listing input clock names. > Required elements: 'pclk', 'hclk' > - Optional elements: 'tx_clk' > + Optional elements: 'tx_clk', 'rx_clk' Please state which compatibles this applies to. > - clocks: Phandles to input clocks. > > Optional properties for PHY child node: -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
