On Tue, May 17, 2016 at 11:18:58PM +0000, Rich Felker wrote: > Signed-off-by: Rich Felker <dalias@xxxxxxxx> > --- > .../devicetree/bindings/timer/jcore,pit.txt | 25 ++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/jcore,pit.txt > > diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt > new file mode 100644 > index 0000000..0f42af4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt > @@ -0,0 +1,25 @@ > +J-Core Programmable Interval Timer and Clocksource > + > +Required properties: > + > +- compatible: Must be "jcore,pit". > + > +- reg: Memory region(s) for timer/clocksource registers. For SMP, > + there should be one region per cpu, indexed by the sequential, > + zero-based hardware cpu number (which is also the logical cpu > + number). One detail I missed: Mark Rutland asked me to remove the corresponding remark about logical cpu numbers from the AIC binding document, so I think it should be removed here too for the same reason -- it's a Linux implementation detail, not part of the hw binding. Rich -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
