On 08/01/2016 08:45 PM, Rich Felker wrote: > Yes. 50 MHz is the natural default frequency, but I found out at the > last minute from the hardware engineers that clocking the current SoC > up to 62.5 MHz (for faster cpu) will require the SPI timing to be > programmed based on the faster reference clock. This messes up the > ability to get optimal SD card transfer rates, so we'll probably end > up having a real 50 MHz clock for the SPI anyway, but I thought it was > important to be able to handle this issue in the DT binding anyway. For those of you following along at home, the first open source VHDL release of http://j-core.org runs at 33 mhz on Spartan 6 FPGAs, the second at 50mhz on the same hardware, and you'd think the third would be 66mhz as the chip continues to be optimized, but one of the new I/O busses requires a multiple of 12.5 mhz and they didn't want to add a clock domain crossing thing for it, hence 62.5 mhz. Earlier it was easy to get everything to work off a single master clock, but as we add more peripherals to the SOC and speed things up stuff's likely to change. (Development is ongoing, and we have a public http://j-core.org/roadmap.html out through 2019. It you're waiting for stuff to stop changing before getting basic board support in that runs on existing releases, it's might be a while.) Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
