On Fri, Jul 01, 2016 at 02:53:52AM +0200, Ondřej Jirman wrote: > On 30.6.2016 22:40, Maxime Ripard wrote: > > Hi, > > > > On Sat, Jun 25, 2016 at 05:45:03AM +0200, megous@xxxxxxxxxx wrote: > >> From: Ondrej Jirman <megous@xxxxxxxxxx> > >> > >> PLL1 on H3 requires special factors application algorithm, > >> when the rate is changed. This algorithm was extracted > >> from the arisc code that handles frequency scaling > >> in the BSP kernel. > >> > >> This commit adds optional apply function to > >> struct factors_data, that can implement non-trivial > >> factors application method, when necessary. > >> > >> Also struct clk_factors_config is extended with position > >> of the PLL lock flag. > > > > Have you tested the current implementation, and found that it was not > > working, or did you duplicate the arisc code directly? > > Also of note is that similar code probably doesn't crash in u-boot, > because there, before changing the PLL1 clock, the cpu is switched to > 24MHz osc, so it is not overclocked, even if factors align in such a way > that you'd get the behavior I described in the other email. That's also something that we can do. See Meson's clk-cpu clock notifiers for example. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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