Hi Mike,
> > if (sdd->port_conf->clk_from_cmu) {
> > + /* There is half-multiplier before the SPI */
> > clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
>
> Just a small comment, but if the fixed-factor divide-by-two clock was
> modeled in Linux, then this driver could call clk_set_rate on that clock
> with the "correct" rate.
>
> I guess that this driver would be the provider of that clock?
Makes sense, I will check it.
Thanks again,
Andi
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