> Wed, Jul 06, 2016 at 04:44:44PM -0700, Iyappan Subramanian wrote:
> Hi Andrew,
>
> On Tue, Jul 5, 2016 at 6:49 AM, Andrew Lunn <andrew@xxxxxxx> wrote:
> > On Mon, Jun 06, 2016 at 10:12:35AM -0700, Iyappan Subramanian wrote:
> >> Hi Andrew,
> >>
> >> Thanks for the review.
> >>
> >> On Tue, May 31, 2016 at 6:11 PM, Andrew Lunn <andrew@xxxxxxx> wrote:
> >> > On Tue, May 31, 2016 at 05:10:38PM -0700, Iyappan Subramanian wrote:
> >> >> +static int xgene_mdio_reset(struct xgene_mdio_pdata *pdata)
> >> >> +{
> >> >> + int ret;
> >> >> +
> >> >> + if (pdata->mdio_id == XGENE_MDIO_RGMII) {
> >> >> + if (pdata->dev->of_node) {
> >> >> + clk_prepare_enable(pdata->clk);
> >> >> + clk_disable_unprepare(pdata->clk);
> >> >> + clk_prepare_enable(pdata->clk);
> >> >
> >> > Hi Iyappan
> >> >
> >> > Is that a workaround for a hardware problem? If so, i would suggest
> >> > adding a comment, to stop people submitting a patch simplifying it.
> >>
> >> Hardware expects this clock sequence. I'll add comment as you suggested.
> >
> > What exactly does the hardware require? Is this a workaround for a bug
> > in the clock generator? Or a workaround for a bug in the MDIO device?
>
> Hardware requires a clock pulse. There is no bug.
And how are you guaranteeing a pulse? You enable/disable/enable
without any sleeps, so it could all happen within a single clock
cycle?
Andrew
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