Hello Scott,
On 2016/5/13 12:37, Scott Wood wrote:
[...]
>
> +#ifdef CONFIG_ARM64
> +static __always_inline void rewrite_tval(const int access,
> + unsigned long evt, struct clock_event_device *clk)
> +{
> + u64 cval_old, cval_new;
> + int timeout = 200;
> +
> + do {
> + cval_old = __arch_counter_get_cntvct();
> + arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
For not memory mapped timer, it will call arch_timer_reg_write_cp15() which has
isb() at the end of arch_timer_reg_write_cp15()...
> + cval_new = __arch_counter_get_cntvct();
So there is isb() between counter retry read, I think it's likely cval_new will
not be equal with cval_old when the cntvct is correct (time lapse is more than
one arch timer cycle).
> + timeout--;
> + } while (cval_old != cval_new && timeout);
> +
> + WARN_ON_ONCE(!timeout);
Then trigger the warning here, correct me if I miss something else.
Thanks
Hanjun
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