On Fri, Jun 24, 2016 at 12:41 PM, Rob Herring <robh@xxxxxxxxxx> wrote: > On Tue, Jun 21, 2016 at 11:25:49PM -0300, Bruno Herrera wrote: >> Signed-off-by: Bruno Herrera <bruherrera@xxxxxxxxx> >> --- >> Documentation/devicetree/bindings/usb/dwc2.txt | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt >> index 20a68bf..79e5370 100644 >> --- a/Documentation/devicetree/bindings/usb/dwc2.txt >> +++ b/Documentation/devicetree/bindings/usb/dwc2.txt >> @@ -11,6 +11,7 @@ Required properties: >> - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; >> - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; >> - snps,dwc2: A generic DWC2 USB controller with default parameters. >> + - st,stm32-fsotg: The DWC2 USB controller instance in STM32F4 SoCs in FS mode; > > This should go above snps,dwc2. > Ok, tks! > What determines FS mode vs. HS? > Its more HW design decision. STM32F429/439/469 has two OTG controllers, one that is FS (internal phy) and other that is HS (but can also work in FS mode with internal/external phy) This bind work with both cores FS and HS working with the internal PHY. I tested the following configurations: 1 - STM32F429I-DISCOv1 board (OTG HS working in FS mode internal PHY) 2 - STM32F469I-DISCO board (OTG FS) I did not tested OTG HS core working in FS mode with external PHY (I2C). >> - reg : Should contain 1 register range (address and length) >> - interrupts : Should contain 1 interrupt >> - clocks: clock provider specifier >> -- >> 2.7.4 (Apple Git-66) >> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
