This adds initial documentation for the pinctrl-msm8x74 driver. Signed-off-by: Bjorn Andersson <bjorn.andersson@xxxxxxxxxxxxxx> --- .../bindings/pinctrl/qcom,msm8x74-pinctrl.txt | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8x74-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8x74-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8x74-pinctrl.txt new file mode 100644 index 0000000..539abd6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8x74-pinctrl.txt @@ -0,0 +1,86 @@ +Qualcomm MSM8x74 TLMM block + +Required properties: +- compatible: "qcom,msm8x74-pinctrl" +- reg: Should be the base address of the TLMM block. +- interrupts: Should be the irq of the TLMM summary interrupt. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. + The first cell is the gpio pin number and the + second cell is used for optional parameters. + +Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Each subnode describes properties for the given pins. + +Required subnode-properties: +- qcom,pins: An array of strings, each matching a pin or group to be + configured. Possible values are listed below. + +Optional subnode-properties: +- qcom,function: A name of the function to be muxed to the specified + pins. Possible values are listed below. +- bias-disable: Configure the specified pins as no pull. +- bias-pull-down: Configure the specified pins as pull down. +- bias-pull-up: Configure the specified pins as pull up. +- drive-strength: Configure the drive strength of the specified pins. + +Note that not all optional properties are valid for all pins. + + +Valid values for qcom,pins are: + gpio0-gpio145 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data + Supports bias and drive-strength + +Valid values for qcom,function are: + blsp_i2c2, blsp_i2c6, blsp_i2c11, blsp_spi1, blsp_uart2, blsp_uart8, slimbus + + (Note that this is not yet the complete list of functions) + + + +Example: + + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8x74-pinctrl"; + reg = <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_default>; + + uart2 { + uart2_default: uart2_default { + mux { + qcom,pins = "gpio4", "gpio5"; + qcom,function = "blsp_uart2"; + }; + + tx { + qcom,pins = "gpio4"; + drive-strength = <4>; + bias-disable; + }; + + rx { + qcom,pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + }; -- 1.8.2.2 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html