On Mon, Jun 13, 2016 at 04:04:32PM -0700, Douglas Anderson wrote:
> As of an earlier change in this series ("Documentation: mmc:
> sdhci-of-arasan: Add ability to export card clock") the SDHCI driver
> used on Rockchip SoCs can now expose its clock. Let's now specify that
> the PHY can use it.
>
> Letting the PHY get access to this clock means it can adjust
> phyctrl_frqsel field appropriately. Although the Rockchip PHY appears
> slightly different than the reference Arasan one, you can see that the
> Arasan datasheet [1] had it defined as:
> Select the frequency range of DLL operation:
> 3b'000 => 200MHz to 170 MHz
> 3b'001 => 170MHz to 140 MHz
> 3b'010 => 140MHz to 110 MHz
> 3b'011 => 110MHz to 80MHz
> 3b'100 => 80MHz to 50 MHz
> 3b'101 => 275Mhz to 250MHz
> 3b'110 => 250MHz to 225MHz
> 3b'111 => 225MHz to 200MHz
>
> On the Rockchip version of the PHY we have less granularity but the idea
> is the same.
>
> [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
>
> Signed-off-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
> ---
> Changes in v2:
> - List out clocks and clock names (Rob)
>
> Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 9 +++++++++
> 1 file changed, 9 insertions(+)
Acked-by: Rob Herring <robh@xxxxxxxxxx>
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