Hi, On Tue, May 10, 2016 at 7:50 PM, Shawn Lin <shawn.lin@xxxxxxxxxxxxxx> wrote: >>> maybe. But I think 180(downside) is the better. > > > NAK my previous comments here. Downside is better for SRD, but won't > work for DDR mode. When running in DDR mode, we should use 90 instead. > > So let me elaborate a bit more here. > For DDR mode, one single clk cycle should sending two data bits outside > to the devices. We need a hold time for both. If 180 is used, the first > bit occurs around the downside area, which won't be sampled by devices > on the upside. So on the upside, the devices will see a zero bit if you > actually send a one-bit, which makes the devices generate CRC finally. > > > For this above, 180 for all SDR mode is ok, but 90 should be deployed > for DDR mode. So simply checking the timing to hardcode it should be > fine. OK, I sent out a patch for 180 always. I can send v2 to use 90 for DDR modes tomorrow. ...or feel free to post that yourself if you want. We want 90 for all DDR modes? So MMC_TIMING_UHS_DDR50, MMC_TIMING_MMC_DDR52, MMC_TIMING_MMC_HS400? (not that we support HS400 in dw_mmc on Rockchip). -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
