On Mon, Apr 25, 2016 at 03:22:41PM +0200, Maxime Ripard wrote: > Hi everyone, > > The Allwinner SoCs (except for the very latest ones) all share the > same set of controllers, loosely coupled together to form the display > pipeline. > > Depending on the SoC, the number of instances of the controller will > change (2 instances of each in the A10, only one in the A13, for > example), and the output availables will change too (HDMI, composite, > VGA on the A20, none of them on the A13). > > On most featured SoCs, it looks like that: > > +--------------------------------------------+ > | RAM | > +--------------------------------------------+ > | | | | > v | | v > +----------------+ | | +----------------+ > | Frontend | | | | Frontend | > +----------------+ | | +----------------+ > | | | | > v | | v > +----------------+ | | +----------------+ > | Backend |<+ +>| Backend | > +----------------+ +----------------+ > | | > v v > +----------------+ +----------------+---> LVDS > | TCON | | TCON |---> RGB > +----------------+ +----------------+ > | +---+ +---+ | > | | | | > v v v v > +------------+ +------------+ +------------+---> VGA > | TV Encoder | | HDMI | | TV Encoder |---> Composite > +------------+ +------------+ +------------+ > > The current code only assumes that there is a single instance of all > the controllers. It also supports only the RGB and Composite > interfaces. > > Let me know what you think, > Maxime > > Changes from v3: > - Fixed a circular dependency issue found when building as a module > - Changed a bit the mode_valid checks > - Fixed an issue with the timings generated by the display engine > > - Changed the DT bindings according to Rob feedback (removed the > allwinner,panel property, documented the endpoints indices, always > use the frontend as the pipeline entrypoint) > > - Changed the display clocks according to Stephen comments (marked > structures as const, changed a variable name) > > Changes from v2: > - Rebased on top of next-20160318 > > - Dropped the generic clock regmap conversion and implemented a > custom clock for our pixel clock, backed by a regmap > - Added the reset bits for the tcon channel 0 and display clocks > - Used the new generic gates compatible for the DRAM gates > - Few clock fixes (missing iounmap, return error checks, etc) > - Found out that the TCON channel 1 clock was not operating properly > because of some weird rounding down and up between the various > generic clocks involved. Rewrote it using custom operations > > - Removed some TODO that were still there > - Converted our panel DT description to the OF graph instead of a > custom property > - Tested the driver on a setup where U-Boot was not initialising the > display, or initialising it on a different output, and fixed a > number of associated bugs (mostly related to missing > initialisation bits, missing reset handles, and so on) > - Fixed the layer code that was assuming that the X and Y > coordinates were in pixels, leading to a miscalculation of the > buffer address when those coordinates where set. > - Added the missing EXPORT_SYMBOL calls > > - Fixed our VBLANK interrupt code that was completely broken (and > not usable, which is why it was unnoticed) > > Changes from v1: > - Rebased on top of 4.4 > > - Merged the clock drivers for the display and TCON channel 0 clocks > - Replaced the container_of calls in the display reset clocks to an > inline function > - Checked the return code of of_clk_parent_fill in the clocks > drivers > - Checked the return code of of_clk_add_provider in the tcon-ch1 and > PLL3 clocks > - Added missing clocks headers > - Created a composite clock unregister function > > - Moved the binding documentation to > Documentation/devicetree/bindings/display > - Added the clocks binding documentation > - Added the Olimex vendor to the list of DT vendors > - Moved to the OF graph representation and the component framework > > - Moved the reset cells count check into the reset framework to > avoid duplicating the code in every xlate implementation. > - Made the reset_ops const > > - Reworked the DRM cmdline mode parsing code to allow named mode > - Fixed the TV mode lookup when the mode name is not present (for > example because it was given by the userspace) > > - Made the driver outputs optional (to avoid crashing when a board > doesn't have either a panel or a composite output enabled) > - Added multiple plane support with transparency > - Moved the backend registers writes commit in the CRTC atomic_flush > callback > - Removed the load / unload functions > - Removed the enabled booleans in my private structure and removed > the implicit call to disable_unused_functions in the DRM core to > push it in the drivers. > - Fixed a few bitmasks on some bitfields definition > - Fixed the RGB connector mode validation that was not testing the > right values Applied the DT patches. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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