On Fri, Apr 29, 2016 at 3:51 AM, Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
> Hi Rob,
>
> On Tue, Mar 8, 2016 at 9:00 AM, Rob Herring <robh@xxxxxxxxxx> wrote:
>> On Mon, Mar 7, 2016 at 5:27 AM, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>>> On Fri, Mar 4, 2016 at 4:13 PM, Rob Herring <robh@xxxxxxxxxx> wrote:
>>>> Sync to upstream dtc commit 53bf130b1cdd ("libfdt: simplify
>>>> fdt_node_check_compatible()"). This adds the following commits from
>>>> upstream:
>>>>
>>>> 53bf130 libfdt: simplify fdt_node_check_compatible()
>>>> c9d9121 Warn on node name unit-address presence/absence mismatch
>>>> 2e53f9d Catch unsigned 32bit overflow when parsing flattened device tree offsets
>>>>
>>>> Signed-off-by: Rob Herring <robh@xxxxxxxxxx>
>>>> ---
>>>> As usual, this is just an automated copy of upstream dtc into the kernel
>>>> tree. The changeset is small enough that I have left it here.
>>>>
>>>> The main reason for this sync is to pick-up the new unit-address
>>>> warnings.
>>>
>>> I gave this a try. Obviously it finds many abuses that should be fixed.
>>>
>>> However, I'm wondering about the following, where the unit-address is just
>>> used to distinguish between multiple instances:
>>>
>>> Warning (unit_address_vs_reg): Node /cache-controller@0 has a unit
>>> name, but no reg property
>>> compatible = "cache";
>>
>> Just add a reg property. The values should probably match the MPIDR in
>> some way (e.g. 0 and 100).
>
> Is it correct to move the cache-controller nodes under the cpus node?
IIRC, the ePAPR^W DTSpec says that is valid.
> Else the reg properties don't match #address/size-cells?
If there's no mmio access then yes, I think under /cpus makes sense.
The ARM /cpus code may throw a warning on this, but we should quiet it
down.
Rob
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