* Tero Kristo <t-kristo@xxxxxx> [160427 04:22]: > On 26/04/16 20:54, J.D. Schroeder wrote: > >From: "J.D. Schroeder" <jay.schroeder@xxxxxxxxxx> > > > >This commit fixes the clock data inside the DRA7xx clocks device tree > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually > >the GMAC_MAIN_CLK and has nothing to do with the register at address > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is > >set to 1 in order to use the GMAC_RMII_CLK instead of the > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: > > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() > > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set > > > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is > >resolved and the clock tree is fixed up. > > > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the > >source clock for the RMII_50MHZ_CLK. > > > >Signed-off-by: J.D. Schroeder <jay.schroeder@xxxxxxxxxx> > >Reviewed-by: Trenton Andres <trenton.andres@xxxxxxxxxx> > > Looks like something weird happened with the clock data conversion tool with > this specific clock. Seems to be the only buggy instance in our clock data > across SoCs. Good catch. > > Acked-by: Tero Kristo <t-kristo@xxxxxx> Applying into omap-for-v4.6/fixes thanks. Tony -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
