On 17:53 Fri 15 Nov , Bo Shen wrote: > Add Atmel PWM controller driver based on PWM framework. > > This is the basic function implementation of Atmel PWM controller. > It can work with PWM based led and backlight. > > Signed-off-by: Bo Shen <voice.shen@xxxxxxxxx> > Acked-by: Alexandre Belloni <alexandre.belloni@xxxxxxxxxxxxxxxxxx> > --- > Changes in v7: > - fix issue for none device tree issues. > > Changes in v6: > - using relaxed version for writel and readl > - add none device tree support > - change some define from lower case to upper case > - split device tree binding document as a separate patch > > Changes in v5: > - call clk_disable directly, if so, it won't cause more than one channel > enabled, the clock can not be disabled. > > Changes in v4: > - check the return value of clk_prepare() > - change channel register size as constant > > Changes in v3: > - change compatible string from "atmel,sama5-pwm" to "atmel,sama5d3-pwm" > - Add PWM led example in binding documentation > - Using micro replace hard code > > Changes in v2: > - Address the comments from Thierry Reding > > drivers/pwm/Kconfig | 9 ++ > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-atmel.c | 380 +++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 390 insertions(+) > create mode 100644 drivers/pwm/pwm-atmel.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index eece329..5043572 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -41,6 +41,15 @@ config PWM_AB8500 > To compile this driver as a module, choose M here: the module > will be called pwm-ab8500. > > +config PWM_ATMEL > + tristate "Atmel PWM support" > + depends on ARCH_AT91 > + help > + Generic PWM framework driver for Atmel SoC. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-atmel. > + > config PWM_ATMEL_TCB > tristate "Atmel TC Block PWM support" > depends on ATMEL_TCLIB && OF > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 8b754e4..1b99cfb 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -1,6 +1,7 @@ > obj-$(CONFIG_PWM) += core.o > obj-$(CONFIG_PWM_SYSFS) += sysfs.o > obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o > +obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o > obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o > obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o > obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o > diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c > new file mode 100644 > index 0000000..d012538 > --- /dev/null > +++ b/drivers/pwm/pwm-atmel.c > @@ -0,0 +1,380 @@ > +/* > + * Driver for Atmel Pulse Width Modulation Controller > + * > + * Copyright (C) 2013 Atmel Corporation > + * Bo Shen <voice.shen@xxxxxxxxx> > + * > + * Licensed under GPLv2. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/pwm.h> > +#include <linux/slab.h> > + > +/* The following is global registers for PWM controller */ > +#define PWM_ENA 0x04 > +#define PWM_DIS 0x08 > +#define PWM_SR 0x0C > +/* Bit field in SR */ > +#define PWM_SR_ALL_CH_ON 0x0F > + > +/* The following register is PWM channel related registers */ > +#define PWM_CH_REG_OFFSET 0x200 > +#define PWM_CH_REG_SIZE 0x20 > + > +#define PWM_CMR 0x0 > +/* Bit field in CMR */ > +#define PWM_CMR_CPOL (1 << 9) > +#define PWM_CMR_UPD_CDTY (1 << 10) > + > +/* The following registers for PWM v1 */ > +#define PWMV1_CDTY 0x04 > +#define PWMV1_CPRD 0x08 > +#define PWMV1_CUPD 0x10 > + > +/* The following registers for PWM v2 */ > +#define PWMV2_CDTY 0x04 > +#define PWMV2_CDTYUPD 0x08 > +#define PWMV2_CPRD 0x0C > +#define PWMV2_CPRDUPD 0x10 > + > +/* Max value for duty and period > + * > + * Although the duty and period register is 32 bit, > + * however only the LSB 16 bits are significant. > + */ > +#define PWM_MAX_DTY 0xFFFF > +#define PWM_MAX_PRD 0xFFFF > +#define PRD_MAX_PRES 10 > + > +struct atmel_pwm_chip { > + struct pwm_chip chip; > + struct clk *clk; > + void __iomem *base; > + > + void (*config)(struct pwm_chip *chip, struct pwm_device *pwm, > + int dty, int prd); > +}; > + > +static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip) > +{ > + return container_of(chip, struct atmel_pwm_chip, chip); > +} > + > +static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip, > + unsigned long offset) > +{ > + return readl_relaxed(chip->base + offset); > +} > + > +static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip, > + unsigned long offset, unsigned long val) > +{ > + writel_relaxed(val, chip->base + offset); > +} > + > +static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip, > + unsigned int ch, unsigned long offset) > +{ > + return readl_relaxed(chip->base + PWM_CH_REG_OFFSET + > + ch * PWM_CH_REG_SIZE + offset); > +} > + > +static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip, > + unsigned int ch, unsigned long offset, > + unsigned long val) > +{ > + writel_relaxed(val, chip->base + PWM_CH_REG_OFFSET + > + ch * PWM_CH_REG_SIZE + offset); > +} > + > +static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, > + int duty_ns, int period_ns) > +{ > + struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip); > + unsigned long clk_rate, prd, dty; > + unsigned long long div; > + int ret, pres = 0; > + > + clk_rate = clk_get_rate(atmel_pwm->clk); > + div = clk_rate; > + > + /* Calculate the period cycles */ > + while (div > PWM_MAX_PRD) { > + div = clk_rate / (1 << pres); > + div = div * period_ns; > + /* 1/Hz = 100000000 ns */ > + do_div(div, 1000000000); > + > + if (pres++ > PRD_MAX_PRES) { > + pr_err("PRES is bigger than maximum pre-scaler\n"); if we have more than 1 pwm with pr_err we can known which is it use dev_xxx instead of all pr_xx with this Ack Best Regards, J. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html