On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote: > The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and > configured through a memory mapped hardware register. > > This same register also configures the MAC interface mode and TX clock > source. Also covered by the register, but not supported in these bindings, > are TX/RX clock delay chains and inverters, and an RMII module. > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> > --- > .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt Acked-by: Rob Herring <robh@xxxxxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
