On Thu, Mar 17, 2016 at 12:57 PM, Rob Herring <robh@xxxxxxxxxx> wrote: > On Thu, Mar 17, 2016 at 12:11 PM, Arnd Bergmann <arnd@xxxxxxxx> wrote: >> On Thursday 17 March 2016 12:06:40 Rob Herring wrote: >>> > diff --git a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt b/Documentation/devicetree/bindings/soc/fsl/guts.txt >>> > similarity index 91% >>> > rename from Documentation/devicetree/bindings/powerpc/fsl/guts.txt >>> > rename to Documentation/devicetree/bindings/soc/fsl/guts.txt >>> > index b71b203..07adca9 100644 >>> > --- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt >>> > +++ b/Documentation/devicetree/bindings/soc/fsl/guts.txt >>> > @@ -25,6 +25,9 @@ Recommended properties: >>> > - fsl,liodn-bits : Indicates the number of defined bits in the LIODN >>> > registers, for those SOCs that have a PAMU device. >>> > >>> > + - little-endian : Indicates that the global utilities block is little >>> > + endian. The default is big endian. >>> >>> The default is "the native endianness of the system". >> >> This may be what is currently documented, but not what we are doing >> in practice, as there is no "native endianess" for either PowerPC or >> ARM -- both allow running big-endian or little-endian kernels and the >> device registers are fixed. > > Notice I said system, not architecture. The way the device registers > are fixed is what I mean by native endianness. I think sometimes it's also hard to define the native endianess of the system too. For whatever reason, we have hardware that having big-endian registers on some on-chip devices but using little-endian registers on other devices. Even if all the devices on certain hardware use registers of the same endianess, it is also hard for the device driver to know what the native endianess really is. > > If the purpose of adding this property now is to support GUTS on the > ARM SoCs, then I'd argue using this property is probably wrong. If the > PPC systems are designed with BE device registers and ARM systems with > LE, then this property is not needed. > >> I think the property here is fine. > > Unless you have studied the FSL ARM based SoCs, then there is not > enough information here to tell. Recent FSL ARM SoCs seems to have more weird endianess issue. :( The same IP could have registers of different endianess on different ARM SoCs. That why we need to define the endianess explicitly in device tree. Regards, Leo -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
