Hi Bharat, I forgot I still have one question here: On Sun, Mar 06, 2016 at 10:02:14PM +0530, Bharat Kumar Gogada wrote: > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > +static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn) > +{ > + struct nwl_pcie *pcie = bus->sysdata; > + > + /* Check link,before accessing downstream ports */ > + if (bus->number != pcie->root_busno) { > + if (!nwl_pcie_link_up(pcie)) > + return false; > + } This seems racy. What if we check, and the link is up, but the link goes down before we actually complete the config access? I'm suggesting that this check for the link being up might be superfluous. The hardware should do something reasonable with the config access if it can't send it down the link. > + > + /* Only one device down on each root port */ > + if (bus->number == pcie->root_busno && devfn > 0) > + return false; > + > + return true; > +} -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html