Hi Kishon,
On 02/24/2016 05:30 PM, Kishon Vijay Abraham I wrote:
Hi Archit,
On Tuesday 23 February 2016 03:06 PM, Archit Taneja wrote:
On 02/23/2016 12:57 AM, Rob Herring wrote:
On Mon, Feb 22, 2016 at 5:07 AM, Archit Taneja <architt@xxxxxxxxxxxxxx> wrote:
On 02/22/2016 08:24 AM, Rob Herring wrote:
On Mon, Feb 15, 2016 at 12:23:26PM +0530, Archit Taneja wrote:
Add HDMI PHY bindings. Update the example to use HDMI PHY.
Add a missing power-domains property in the HDMI core bindings.
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Archit Taneja <architt@xxxxxxxxxxxxxx>
---
.../devicetree/bindings/display/msm/hdmi.txt | 39
+++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt
b/Documentation/devicetree/bindings/display/msm/hdmi.txt
index 379ee2e..4d71910 100644
--- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
+++ b/Documentation/devicetree/bindings/display/msm/hdmi.txt
@@ -11,6 +11,7 @@ Required properties:
- reg: Physical base address and length of the controller's registers
- reg-names: "core_physical"
- interrupts: The interrupt signal from the hdmi block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
@@ -18,6 +19,7 @@ Required properties:
- qcom,hdmi-tx-hpd-gpio: hpd pin
- core-vdda-supply: phandle to supply regulator
- hdmi-mux-supply: phandle to mux regulator
+- qcom,hdmi-phy: phandle to HDMI PHY device node
Why not use the generic phy binding?
You'd asked about this in the first version of this patch. You
probably missed reading my reply. Partially my fault since I
missed out putting the "In-Reply-to" when posting this set. I've
mentioned the reason again here:
The PHY in the HDMI and DSI blocks can't be implemented using the
common phy framework. The PHY blocks have a PLL sub-block within
them which acts as a pixel clock source for the display processor
block.
That sounds like a problem with the common phy framework, not the DT
binding. Nothing says you have to use the common phy f/w if you use
the phy binding. I say that as the binding maintainer. As a kernel
developer, I would say fix the common phy framework to handle this
case. However, I don't think anything prevents the phy driver from
registering both a phy and a clock.
Okay. For some reason, I thought it would be wrong to use the same
common phy bindings but use our own phy driver.
I will convert the bindings to the generic phy binding.
This dependency causes the need to split the phy power on sequence
into 2 parts (one to enable resources to enable the PLL, and the
other to enable the phy itself), which the phy framework can't
do. That's the main reason not to use it. There are some more
complex use cases for DSI PHY (drive two PHYs with the same
DSI PLL) which the phy framework can't support.
Doesn't the phy framework already support the former? It has power on
and init calls. Personally, I find the split there ill-defined.
I always assumed that the init/exit ops were something that you would
call just once (during probe/remove) and then forget about it. I only
right, the phy ops were intended to be used that way. However because of
different sequence requirements for different controllers, that's not followed
always.
now noticed that init and power_on are often paired together (as are
power_off and exit). I went through the common phy framework code in
more detail, but I realized I would face the following issue:
I was looking for the sequence:
1. enable PHY resources (enables clocks/regulators/pm_runtime_get_sync)
get_sync is invoked by the phy core during phy_init and phy_power_on (it was
done basically to access registers that have to be configured during init and
power on). regulator is enabled during phy_power_on and clocks (opt func
clocks) should be enable during runtime callbacks in the driver (main clock is
enabled as part of get_sync).
2. set_rate/enable the PLL clock provided by PHY
If the PHY is the source of clock, then the PHY should also be modeled as clock
provider. (see rockchip-usb PHY)
3. enable PHY (configure some PHY registers)
the general configuration of the PHY should go in phy_init (e.g any calibration
settings) and registers to power_on the PHY should go in phy_power_on.
Thanks for the input. I currently have a custom hdmi phy driver, which
is a clock provider too. The PLL clock provided by the PHY can't be
configured (clk_set_rate, enabe etc.) unless we enable some of the PHY
interface clocks and other resources (enabled via pm_runtime_get_sync).
These resources need to be left on for the clock to be configured
successfully. The only way I can think of mapping my code with the
phy ops that satisfies the above requirements will result in the
following sequence:
...
phy_power_on(phy);
clk_set_rate(pll);
clk_prepare_enable(pll);
phy_init(phy);
...
This would be a bit of a misuse. To make things more complicated, some
of the PHY register need to be configured in a sequence which also
contains PLL registers. So, instead of these being in
phy_init/phy_power_on, they have to be in the PLL's clock
ops, which sort of makes things even more vague.
I would go with my custom hdmi phy implementation for now using generic
phy bindings, but I'll try to investigate more on what can be done to
get this running using the common phy f/w.
Thanks,
Archit
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