Quoting Lars Persson (2016-02-14 00:03:06)
>
>
> On 02/12/2016 05:39 PM, Rob Herring wrote:
> > On Thu, Feb 11, 2016 at 05:01:03PM +0100, Lars Persson wrote:
> >> Add device tree documentation for the main PLL in the Artpec-6 SoC.
> > Roughly how many clocks does this SoC have?
> It will have 17 clocks declared in the device tree and three
> SoC-specific clock drivers.
Are all of those clks going to individual DT nodes with clock-cells = 0?
If so, I wonder if you should be targeting a clock-controller style
binding description, with a node that represents the clock-controller IP
block, with clock-cells >= 1. It really comes down to whether or not
these clock controls exist in the same IP block.
You mentioned three distinct clock drivers. So possibly three clock
controller nodes in DT then?
Is there a reference manual/register map available for this SoC?
>
> >
> >> Signed-off-by: Lars Persson <larper@xxxxxxxx>
> >> ---
> >> Documentation/devicetree/bindings/clock/artpec6.txt | 16 ++++++++++++++++
> >> 1 file changed, 16 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt
> >> new file mode 100644
> >> index 0000000..521fec8
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/artpec6.txt
> >> @@ -0,0 +1,16 @@
> >> +* Clock bindings for Axis ARTPEC-6 chip
Please specify that this is based on the clock provider binding in
Documentation/devicetree/bindings/clock/clock-bindings.txt
Regards,
Mike
> >> +
> >> +Required properties:
> >> +- #clock-cells: Should be <0>
> >> +- compatible: Should be "axis,artpec6-pll1-clock"
> >> +- reg: Address and length of the DEVSTAT register.
> >> +- clocks: The PLL's input clock.
> >> +
> >> +Examples:
> >> +
> >> +pll1_clk: pll1_clk {
> >> + #clock-cells = <0>;
> >> + compatible = "axis,artpec6-pll1-clock";
> >> + reg = <0xf8000000 4>;
> >> + clocks = <&ext_clk>;
> >> +};
> >> --
> >> 2.1.4
> >>
>
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