Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
v3:
- Drop "arm,data-latency" and "arm,tag-latency" properties, as they
may not be valid when using virtualization,
- Change one-line summary prefix to match current arm-soc practices,
v2:
- Drop (incorrect) optional cache-{size,sets,{block,line}-size}
properties, as this information is auto-detected,
- Integrate linking CPUs to L2 cache into this patch,
- Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
SYSC PM Domain DT Support".
---
arch/arm/boot/dts/r8a7791.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 8910236e64bf93ed..a65910ed5884edfd 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -51,6 +51,7 @@
voltage-tolerance = <1>; /* 1% */
clocks = <&cpg_clocks R8A7791_CLK_Z>;
clock-latency = <300000>; /* 300 us */
+ next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
operating-points = <1500000 1000000>,
@@ -66,9 +67,16 @@
compatible = "arm,cortex-a15";
reg = <1>;
clock-frequency = <1500000000>;
+ next-level-cache = <&L2_CA15>;
};
};
+ L2_CA15: cache-controller@0 {
+ compatible = "cache";
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
1.9.1
--
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