On Thu, Jan 14, 2016 at 08:56:31PM -0800, Caleb Crome wrote: > On Thu, Jan 14, 2016 at 6:45 PM, Nicolin Chen <nicoleotsuka@xxxxxxxxx> wrote: > > On Thu, Jan 14, 2016 at 01:26:24PM -0800, Caleb Crome wrote: > > > >> As for optimal settings, I finally came to a setting of 4 for depth & > >> maxburst, which will result in more DMA requests, but it's the only > >> way that works at 48kHz for me. The default settings is 13 (15 - 2) > >> for the ones of the 15 item fifo, which is a pretty dramatic > >> difference. I just don't know if other chips will behave badly in > >> that case. > > > > What's your final configuration for TFWM0 bits, 4? > > Yes, a value of 4 for my use case: i.MX6 @ 768000 words/second (48khz > * 16 channels). 4 means there are >= 4 empty slots in the FIFO, so there are no more than 11 remaining data. This makes sense. IIRC, the Freescale official BSP release for i.MX is used to set 6 to TFWM0/1 in the old day, not sure about recent ones though. So I think setting 4 to TFWM0/1 should work for most of cases. We may also let others test it before merging it. Actually a setting of 13 is much more risky in my opinion. It means only two empty slots in the FIFO, so it might be easily to get under/ overflow if a DMA transaction gets delay somehow. The only benefit is that DMA requests and interrupt (FIQ) can be reduced. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
