On 14/01/16 14:14, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Fri, Dec 04, 2015 at 02:57:10PM +0000, Jon Hunter wrote: >> For Tegra124 and Tegra210, the GPU partition cannot be toggled on and off >> via the APBDEV_PMC_PWRGATE_TOGGLE_0 register. For these devices, the >> partition is simply powered up and down via an external regulator. >> Describe in the PMC SoC data in which devices the GPU partition can be >> controlled via the APBDEV_PMC_PWRGATE_TOGGLE_0 register and ensure that >> no one can incorrectly try to toggle the GPU partition via the >> APBDEV_PMC_PWRGATE_TOGGLE_0 register. >> >> Signed-off-by: Jon Hunter <jonathanh@xxxxxxxxxx> >> --- >> drivers/soc/tegra/pmc.c | 11 +++++++++++ >> 1 file changed, 11 insertions(+) > > The TRM doesn't mention anything like this. Will this be updated in the > TRM as well? For T210, I have requested that the partitions are updated. Looks like the powergate sequencing information for T210 is still missing from the TRM. I can request that this is added. I will make a note for T124 as well as it is missing. Cheers Jon -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
