On Thu, Jan 14, 2016 at 04:24:51PM +0100, Maxime Ripard wrote: > The Allwinner SoCs have a gate controller to gate the access to the DRAM > clock to the some devices that need to access the DRAM directly (mostly > display / image related IPs). > > Use a simple gates driver to support the one found in the A13 / R8 SoCs. > > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxxxxxxxxx> > Acked-by: Chen-Yu Tsai <wens@xxxxxxxx> > --- > Documentation/devicetree/bindings/clock/sunxi.txt | 1 + Acked-by: Rob Herring <robh@xxxxxxxxxx> > drivers/clk/sunxi/clk-simple-gates.c | 2 ++ > 2 files changed, 3 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
