On Tue, Dec 15, 2015 at 4:49 PM, Gilad Avidov <gavidov@xxxxxxxxxxxxxx> wrote: > On Mon, 14 Dec 2015 17:39:09 -0800 > Florian Fainelli <f.fainelli@xxxxxxxxx> wrote: > >> On 14/12/15 16:19, Gilad Avidov wrote: >> >> [snip] >> >> > + "sgmii_irq"; >> > + qcom,emac-gpio-mdc = <&msmgpio 123 0>; >> > + qcom,emac-gpio-mdio = <&msmgpio 124 0>; >> > + qcom,emac-tstamp-en; >> > + qcom,emac-ptp-frac-ns-adj = <125000000 1>; >> > + phy-addr = <0>; >> >> Please use the standard Ethernet PHY and MDIO device tree bindings to >> describe your MAC to PHY connection here, that includes using a >> phy-connection-type property to describe the (x)MII lanes. >> > > > Hi Florian, > > Thank you for the review. > > Unfortunately this Ethernet controller's PHY is non standard and fits > poorly into the standard MDIO framework layer. Rather than read/writs > over MDIO only, this hw have some of the PHY registers internal and > accessed by memory mapped IO, while others are accessed over the MDIO. > Some standard functions requires using both. Additionally a number > of different functions are controlled from different fields of the > same register. Even so, the bindings should follow the standard binding for MDIO bus whether you can use the common kernel infrastructure or not. Having internal phy connected to external phy is pretty common for 10G. Not sure if that is what you mean here or not. Rob -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
