From: Shaohui Xie <Shaohui.Xie@xxxxxxxxxxxxx> PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs to change corresponding serdes lane settings, so a reference is needed for serdes lane. This patch describes properties needed for PCS PHY to support backplane. Signed-off-by: Shaohui Xie <Shaohui.Xie@xxxxxxxxxxxxx> --- based on: http://patchwork.ozlabs.org/patch/560936/ Documentation/devicetree/bindings/powerpc/fsl/fman.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt index 55c2c03..b38e727 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/fman.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/fman.txt @@ -432,6 +432,16 @@ example of how to define a PHY (Internal PHY has no interrupt line). - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY. - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY, PCS PHY addr must be '0'. + PCS PHY can support backplane (1000BASE-KX and 10GBASE-KR), this needs to + change the corresponding serdes lane settings. + + PCS PHY node properties required for backplane: + + - compatible: must be "ethernet-phy-ieee802.3-c45". + - phy-mode: string, operation mode of the PHY interface; must be "1000base-kx" + for 1000BASE-KX, or "10gbase-kr" for 10GBASE-KR. + - lane-handle: phandle, specifies a reference to a node representing a Serdes. + - lane-range: offset and length of the register set for the serdes lane. EXAMPLE @@ -464,7 +474,11 @@ mdio@f1000 { fsl,fman-internal-mdio; pcsphy6: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "10gbase-kr"; reg = <0x0>; + lane-handle = <&serdes>; + lane-range = <0x18c0 0x40>; }; }; -- 2.1.0.27.g96db324 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
