On 18.12.2015 12:03, Geert Uytterhoeven wrote:
Hi Dirk,
On Sat, Dec 12, 2015 at 8:16 AM, Dirk Behme <dirk.behme@xxxxxxxxx> wrote:
From: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Signed-off-by: Dirk Behme <dirk.behme@xxxxxxxxx>
---
Note: Geert: I picked your patch from
http://www.spinics.net/lists/arm-kernel/msg466628.html
incoporated some review comments and rebased it against
https://git.kernel.org/cgit/linux/kernel/git/horms/renesas.git/log/?h=next renesas-next-20151211v2-v4.4-rc1
This is more or less what I have locally, except that I kept the latency
properties
Hmm, maybe I missed anything, but the only part reading the latency I
can find is
arch/arm/mm/cache-l2x0.c
[1] which isn't relevant for arm64?
Best regards
Dirk
[1]
./arch/arm/mm/cache-l2x0.c:1042: of_property_read_u32(np,
"arm,tag-latency", &tag);
./arch/arm/mm/cache-l2x0.c:1143: of_property_read_u32_array(np,
"arm,tag-latency", tag, ARRAY_SIZE(tag));
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