On 11.12.2015 14:07, Chanwoo Choi wrote: > This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has > one power line for all buses to translate data between DRAM and sub-blocks. > > Following list specifies the detailed relation between DRAM and sub-blocks: > - DMC/ACP clock for DMC (Dynamic Memory Controller) > - ACLK200 clock for LCD0 > - ACLK100 clock for PERIL/PERIR/MFC(PCLK) > - ACLK160 clock for CAM/TV/LCD0/LCD1 > - ACLK133 clock for FSYS/GPS > - GDL/GDR clock for LEFTBUS/RIGHTBUS > - SCLK_MFC clock for MFC > > Signed-off-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> > --- > arch/arm/boot/dts/exynos4210.dtsi | 159 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 159 insertions(+) > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
