On 11.12.2015 14:07, Chanwoo Choi wrote: > This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. > Exynos3250 has following AXI buses to translate data between > DRAM and sub-blocks. > > Following list specifies the detailed relation between DRAM and sub-blocks: > - ACLK400 clock for MCUISP > - ACLK266 clock for ISP > - ACLK200 clock for FSYS > - ACLK160 clock for LCD0 > - ACLK100 clock for PERIL > - GDL clock for LEFTBUS > - GDR clock for RIGHTBUS > - SCLK_MFC clock for MFC > > Signed-off-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx> > --- > arch/arm/boot/dts/exynos3250.dtsi | 147 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 147 insertions(+) > Reviewed-by: Krzysztof Kozlowski <k.kozlowski@xxxxxxxxxxx> Best regards, Krzysztof -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
