Add a device node for the L2 cache, and link the CPU node to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and requires the following settings:
- Tag RAM latency: 3 cycles,
- Data RAM latency: 4 cycles,
- Data RAM setup: 0 cycles.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
What are the DT bindings for a Cortex-A15 L2 cache controller?
v2:
- Drop (incorrect) optional cache-{size,sets,{block,line}-size}
properties, as this information is auto-detected,
- Integrate linking CPU to L2 cache into this patch,
- Extracted from series "[PATCH/RFC 00/15] ARM: shmobile: R-Car: Add
SYSC PM Domain DT Support".
---
arch/arm/boot/dts/r8a7793.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 33205ecb2a596979..59f8a4fcda1dee95 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -42,9 +42,18 @@
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
+ next-level-cache = <&L2_CA15>;
};
};
+ L2_CA15: cache-controller@0 {
+ compatible = "cache";
+ arm,data-latency = <4 4 0>;
+ arm,tag-latency = <3 3 3>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
1.9.1
--
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