On 29/11/15 12:03, Bharat Kumar Gogada wrote: > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > Signed-off-by: Bharat Kumar Gogada <bharatku@xxxxxxxxxx> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xxxxxxxxxx> > Acked-by: Rob Herring <robh@xxxxxxxxxx> I don't have much to add to this, so FWIW: Reviewed-by: Marc Zyngier <marc.zyngier@xxxxxxx> M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
