Re: [PATCH v2 5/5] stmmac: socfpga: Provide dt node to config ptp clk source.

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On Monday 07 December 2015 21:34:29 Phil Reid wrote:
> On 7/12/2015 5:05 PM, Arnd Bergmann wrote:
> > On Monday 07 December 2015 09:38:44 Phil Reid wrote:
> >> Signed-off-by: Phil Reid <preid@xxxxxxxxxxxxxxxxx>
> >> ---
> >>   Documentation/devicetree/bindings/net/socfpga-dwmac.txt | 2 ++
> >>   drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c     | 9 +++++++++
> >>   2 files changed, 11 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> >> index 3a9d679..72d82d6 100644
> >> --- a/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> >> +++ b/Documentation/devicetree/bindings/net/socfpga-dwmac.txt
> >> @@ -11,6 +11,8 @@ Required properties:
> >>                    designware version numbers documented in stmmac.txt
> >>    - altr,sysmgr-syscon : Should be the phandle to the system manager node that
> >>      encompasses the glue register, the register offset, and the register shift.
> >> + - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
> >> +   for ptp ref clk. This affects all emacs as the clock is common.
> >>
> >
> > Is this feature specific to the Altera glue logic, or would it be possible
> > to do the same thing on another dwmac implementation?
> >
> I think it is specific to Altera's glue logic. It selects either a clock connected
> directly to the ARM HPS core or a clock routed from Altera FPGA fabric.
> Control register is in the altera sysmgr.
> 
> 

Ok, makes sense.

	Arnd
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