On Sat, Dec 05, 2015 at 09:16:42PM +0800, Chen-Yu Tsai wrote: > The A10/A20 share the same set of DRAM clock gates, which controls > direct memory access for some peripherals. > > On the A10, bit 15 controls the system's DRAM clock output (possibly > to the DRAM chips), which we need to keep on. > > On the A20 this has been moved to the DRAM controller, becoming a no-op. > However it is still listed in the user manual, so add it anyway. > > Signed-off-by: Chen-Yu Tsai <wens@xxxxxxxx> Applied, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com
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